Method of forming self-aligned thin film transistor

ABSTRACT

During the formation of a self-aligned thin film transistor (50), the semiconductor material channel layer (58) on the gate insulating layer (56) has a passivation shield (P S ) applied to it aligned with the gate electrode (54). The channel layer is then exposed to a reagent selected to yield a chemical reaction with the portions of the channel layer (58) not covered by the passivation shield (P S ) causing removal of a component of the semiconductor material thereby to change the electrical properties of those portions of the channel layer. In this manner, doped source and drain regions (60, 62) can be formed on opposite sides of the channel having edges that extend to the edges of the gate electrode avoiding any overlap therebetween and reducing the parasitic capacitance of the thin film transistor (50).

TECHNICAL FIELD

The present invention relates to semiconductor fabrication methods andin particular to a method of doping a compound semiconductor material.More specifically, the present invention relates to a method of forminga self-aligned thin film transistor (TFT).

BACKGROUND ART

Self-aligned field effect transistors (FETS) are known in the art.During the formation of transistors of this nature, ion implantation hasbeen used to form the heavily doped source and drain regions of thetransistor so that the edges of the source and drain regions line upwith the edges of the gate electrode. This doping of the source anddrain regions is of course necessary since these regions are unmodulatedby the gate electrode. Since there is no overlap of the source and drainregions with the gate electrode, the parasitic capacitance of thetransistor is greatly reduced as compared to conventional transistorshaving gate electrodes and source and drain regions that overlap.

Parasitic capacitance affects the switching speed of a transistor.Therefore, in environments requiring high speed switching, such as indriver circuits for active matrix liquid crystal displays (AMLCDs), itis desired to minimize the parasitic capacitance of transistors toincrease their switching speed. Although ion implantation methodologyhas allowed self-aligned transistors which reduce parasitic capacitanceto be fabricated, ion implantation is a high energy process.Accordingly, alternative methods of doping semiconductor material andfabricating self-aligned transistors which reduce energy requirementsare desired.

Therefore, it is an object of the present invention to provide a novelmethod of doping compound semiconductor material and a novel method offorming a self-aligned thin film transistor.

DISCLOSURE OF THE INVENTION

According to one aspect of the present invention there is provided amethod of doping a compound semiconductor material comprising the stepof:

exposing the compound semiconductor material to a reagent selected toyield a chemical reaction with the semiconductor material causingremoval of a component of said semiconductor material thereby to changeits electrical properties and dope said semiconductor material.

According to another aspect of the present invention there is provided amethod of forming a self-aligned thin film transistor comprising thesteps of:

depositing a gate electrode on a surface of a glass substrate andcovering said surface and gate electrode with a gate insulating layer;

depositing a channel layer formed of compound semiconductor material onsaid gate insulating layer, said channel layer being positioned over andextending beyond said gate electrode;

depositing a shield on a portion of said channel layer aligned with andoverlying said gate electrode;

subjecting the structure to a reagent selected to react with saidsemiconductor material causing removal of a component thereof, saidreagent reacting with the portions of said channel layer not covered bysaid shield to form doped source and drain regions extending to theedges of said gate electrode and positioned on opposite sides of achannel; and

forming source and drain electrodes in contact with said respectivesource and drain regions.

In yet another aspect of the present invention there is provided in aself-aligned thin film transistor fabrication method wherein a gateelectrode is deposited on a substrate, said substrate and gate electrodeare covered by a gate insulating layer, a channel and doped source anddrain regions on opposite sides of said channel are deposited on saidgate insulting layer and source and drain electrodes are formed andcontact the respective source and drain region, the improvementcomprising:

depositing a channel layer formed of a compound semiconductor materialon said gate insulating layer;

shielding a portion of said channel layer overlying and aligned withsaid gate electrode; and

doping portions of said channel layer not shielded by exposing theportions to a reagent selected to yield a chemical reaction with saidcompound semiconductor material causing removal of a component of saidsemiconductor material thereby to change its electrical properties anddefine said doped source and drain regions.

In still yet another aspect of the present invention there is provided amethod of forming a self-aligned thin film transistor, wherein a gateinsulating layer covers a gate electrode and a surface of a glasssubstrate, said method comprising the steps of:

depositing a channel layer formed of compound semiconductor material onsaid gate insulating layer, said channel layer being positioned over andextending beyond said gate electrode;

forming a shield over a portion of said channel layer aligned with andoverlying said gate electrode;

subjecting the structure to a reagent selected to react with saidsemiconductor material causing removal of a component thereof, saidreagent reacting with the portions of said channel layer not covered bysaid shield to form doped source and drain regions extending to theedges of said gate electrode and positioned on opposite sides of achannel; and

placing source and drain electrodes in contact with said respectivesource and drain regions.

Preferably, the compound semiconductor material is formed of one ofCdSe, CdTe, CdS, InP and GaP. It is also preferred that the reagent isin the form of one of a gas, plasma or liquid chemical reagent.

The present invention provides advantages in that a low temperature andlow energy process is used to fabricate a self-aligned transistor whichmakes use of the fact that most compound semiconductor materials willreact with a reagent causing removal of one of the components of thesemiconductor material and thereby causing the electrical properties ofthe semiconductor material to change.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the present invention will now be described more fullywith reference to the accompanying drawings in which:

FIGS. 1a, 1b and 1c are cross-sectional views of various prior art thinfilm transistors having inverted staggered structures;

FIG. 2 is a cross-sectional view of a self-aligned thin film transistorhaving an inverted staggered structure and formed in accordance with thepresent method;

FIGS. 3a to 3f show fabrication steps performed during the formation ofthe thin film transistor of FIG. 2;

FIG. 4 is a cross-sectional view of an alternative embodiment of aself-aligned thin film transistor formed in accordance with the presentmethod;

FIGS. 5a and 5b show fabrication steps performed during the formation ofthe thin film transistor of FIG. 4; and

FIG. 6 is a cross-sectional view of yet another embodiment of aself-aligned thin film transistor formed in accordance with the presentmethod.

BEST MODES FOR CARRYING OUT THE INVENTION

FIGS. 1a to 1c show a number of prior art thin film transistors T, eachhaving an inverted staggered structure. Each transistor includes asubstrate ST, a gate insulating layer GI and a semiconductor materialchannel C defining the source and drain regions of the transistor.Source and drain electrodes S and D respectively are located on the gateinsulating layer adjacent the source and drain regions. A gate electrodeG is located between the substrate and the gate insulating layer. Ineach of these transistors T, there is an overlap between the source anddrain electrodes and the gate electrode. It is this overlap which isresponsible for parasitic capacitance.

FIG. 2 shows a self-aligned thin film transistor fabricated inaccordance with the present method and is indicated generally byreference numeral 50. As can be seen, the transistor 50 includes a glasssubstrate 52 on which a Cr gate electrode 54 is located. A gateinsulating layer 56 formed of SiO₂ overlies the gate electrode 54 andone surface of the glass substrate 52. A compound polycrystallinesemiconductor material channel 58 formed of Cadmium Selenide (CdSe) ison the gate insulating layer 56 above the gate electrode. Doped sourceand drain regions 60 and 62 respectively formed of semiconductormaterial are on opposite sides of the channel 58. A passivation layer 64in the form of a positive photoresist covers the source and drainregions 60 and 62, the channel 58 and the gate insulating layer 56.Source and drain electrodes 66 and 68 are located on the passivationlayer 64 and contact a respective one of the source and drain regions 60and 62 through vias 70 formed in the passivation layer.

The present method of forming the transistor 50 will now be describedwith particular reference to FIGS. 3a to 3f. During the fabricationprocess, after the gate electrode 54 and gate insulating layer 56 havebeen deposited on the glass substrate 52 (see FIG. 3a), a channel layer58 is deposited on the gate insulating layer 56 (see FIG. 3b). As can beseen, the channel layer overlies and extends beyond the gate electrode54. A passivation shield P_(S) in the form of a positive photoresist isthen deposited over the channel layer 58 and the gate insulating layer56.

The structure is then exposed to UV radiation from the rear side (seeFIG. 3c). The glass substrate 52, gate insulating layer 56 and channellayer 58 are transparent; however, the gate electrode 54 is opaque.Because of this, only the portion of the passivation shield P_(S)overlying and aligned with the gate electrode 54 polymerizes. Afterthis, the portion of the passivation shield P_(S) that does notpolymerize is removed.

Following this, the structure is exposed to a reagent selected to reactwith the semiconductor material forming the channel layer 58 which willcause removal of a component of the semiconductor material and therebychange its electrical properties in the desired manner (see FIG. 3d).The passivation shield P_(S) prevents the portion of the channel layer58 located directly below it from being exposed to the reagent.Therefore, the electrical properties of the portion of the channel layer58 aligned with the gate electrode 54 remain unchanged. However, theportions of the channel layer 58 that are not covered by the passivationshield P_(S) react with the reagent. In this example, since the channellayer 58 is formed of CdSe, the CdSe layer is exposed to a Hydrogen (H)plasma reagent yielding a chemical reaction which selectively removesSelenium (Se) causing Selenium vacancies to be present in thepolycrystalline semiconductor material (ie. CdSe+H→Cd+H₂ Se). TheSelenium vacancies result in the semiconductor material becoming highlyn⁺ type (i.e. doped).

During this stage of the process, it is important to subject thesemiconductor material to the reagent so that the semiconductor materialbecomes heavily doped. The parameters which affect the reaction betweenthe reagent and the semiconductor material are exposure time,temperature, power and reagent concentration. By adjusting the reagentconcentration, the exposure time can be set to give an adequate exposuretime window.

Prior to performing this stage, calibration tests are performed onsemiconductor material to determine the values of the parametersnecessary to achieve the desired doping concentration while maintainingthe desired exposure time window. Once the values of the parameters havebeen determined, they are used when subjecting the semiconductormaterial channel layer to the reagent.

Since the passivation shield P_(S) is aligned with the gate electrode54, the portions of the channel layer 58 on opposite sides of thepassivation shield that undergo changes in electrical properties (i.e.become heavily doped), define the source and drain regions of thetransistor 50 and have edges that line up with the edges of the gateelectrode (FIG. 3e). In this way, there is no overlap of the source anddrain regions with the gate electrode thereby reducing the parasiticcapacitance of the transistor.

Once the source and drain regions have been formed, the passivationshield P_(S) is removed and the structure is covered with a passivationlayer 64 (also see FIG. 3e). Contact vias 70 are formed in thepassivation layer 64 above the source and drain regions 60 and 62respectively and the source and drain electrodes 66 and 68 respectivelyare then formed to complete the thin film transistor.

Referring now to FIG. 4, a self-aligned film transistor fabricated usingan alternative embodiment of the present method is shown. In thisembodiment, like reference numerals will be used to indicate likecomponents with a "100" added for clarity. In this embodiment, thetransistor 150 is very similar to that shown in FIG. 2 and includes aglass substrate 152, a gate electrode 154, a gate insulating layer 156and a compound semiconductor material channel 158. Doped source anddrain regions 160 and 162 respectively formed of semiconductor materialare on opposite sides of the channel 158. Overlying the channel 158 andaligned with the gate electrode 154 is a shield 200 formed of SiO₂. Apassivation layer 164 covers the gate insulating layer 156, source anddrain regions 160 and 162 and the passivation shield 200. Source anddrain electrodes 166 and 168 contact a respective one of the source anddrain regions 160 and 162 through vias 170 formed in the passivationlayer 164.

During formation of transistor 150, after the gate electrode 154, gateinsulating layer 156 and channel layer have been formed on the substrate152 and prior to exposing the structure to UV radiation, the structureis covered with a layer 200 of SiO₂ and then with a passivation shieldP_(S) in the form of a positive photoresist. The structure is thenexposed to UV radiation causing the photoresist aligned with andoverlying the gate electrode to polymerize (see FIG. 5a). Once this hasbeen done, the portion of the passivation shield P_(S) that does notpolymerize is removed and the exposed SiO₂ layer is etched from thestructure. Following this, the structure is treated in the mannerdescribed previously by exposing the structure to a suitable reagent(see FIG. 5b) and completing steps (iv) and (v) shown in FIGS. 3e and3f.

If desired during the fabrication process, step (iv) illustrated in FIG.3e may be omitted so that once the structure has been subjected to thereagent to remove selectively a component of the semiconductor materialto form the doped source and drain regions and the passivation shieldhas been removed from the structure, the source and drain electrodes canbe formed directly on the respective source and drain regions and thegate insulating layer. FIG. 6 shows a self-aligned thin film transistorformed in this manner. As can be seen, transistor 350 is very similar tothose previously described except that the passivation layer has beenremoved avoiding the need to form contact vias.

Although the gate electrode has been described as being formed ofChromium, it should be realized that any refractory metal or combinationof refractory and high conductivity metals are suitable. The gateinsulating layer may also be formed of materials other than SiO₂ such asfor example Si₃ N₄ or any other dielectric material suitable for formingan isolation layer in a field effect transistor.

As one of skill in the art will appreciate, the channel layer must beformed of a compound semiconductor material which reacts with a reagentto yield a chemical reaction which selectively removes a component ofthe semiconductor material. Although the preferred embodiment describesthe semiconductor material as being CdSe, other compound semiconductormaterials can be used such as for example CdS, CdTe, InP and GaP. Thereagent will of course be selected based on the type of compoundsemiconductor material forming the channel layer and may be a gas,plasma or liquid chemical reagent.

The preferred embodiments of the present invention have been describedduring formation of self-aligned thin film transistors. However, thoseof skill in the art will appreciate that the present method of dopingcompound semiconductor material can be used during the formation ofvirtually any semiconductor device.

When the thin film transistors are for use in an active matrix liquidcrystal display or a flat panel detector for radiation imaging, an arrayof the transistors is formed simultaneously on a common substrate. Thoseof skill in the art will appreciate that the various layers forming thearray of transistors are deposited on the substrate and etched asrequired.

Those of skill in the art will also appreciate that variousmodifications may be made to the present invention without departingfrom its scope as defined by the appended claims.

What is claimed is:
 1. A method of forming a self-aligned thin filmtransistor comprising the steps of:depositing a gate electrode on asurface of a glass substrate and covering said surface and gateelectrode with a gate insulating layer; depositing a channel layerformed of compound semiconductor material on said gate insulating layer,said channel layer being positioned over and extending beyond said gateelectrode; depositing a shield on a portion of said channel layeraligned with and overlying said gate electrode; subjecting the structureto a reagent selected to react with said semiconductor material causingremoval of a component thereof, said reagent reacting with the portionsof said channel layer not covered by said shield to form doped sourceand drain regions extending to the edges of said gate electrode andpositioned on opposite sides of a channel; and forming source and drainelectrodes in contact with said respective source and drain regions. 2.The method of claim 1 wherein said shield is formed on said channellayer using positive photoresist.
 3. The method of claim 2 wherein priorto forming said source and drain electrodes, said shield is removed anda passivation layer is placed over said drain and source regions, saidchannel and said gate insulating layer, said drain and source electrodescontacting said respective source and drain regions through vias formedin said passivation layer.
 4. The method of claim 1 wherein a layer ofSiO₂ is formed on said channel layer interposed between said channellayer and said shield.
 5. The method of claim 1 wherein saidsemiconductor material is formed of one of CdSe, CdTe, CdS, InP and GaP.6. The method of claim 1 wherein said reagent is in the form of one of agas, plasma and liquid chemical reagent.
 7. A self-aligned thin filmtransistor fabrication method wherein a gate electrode is deposited on asubstrate, said substrate and gate electrode are covered by a gateinsulating layer, a channel and doped source and drain regions onopposite sides of said channel are deposited on said gate insulatinglayer and source and drain electrodes are formed and contact therespective source and drain region, the improvementcomprising:depositing a channel layer formed of a compound semiconductormaterial on said gate insulating layer; shielding a portion of saidchannel layer overlying and aligned with said gate electrode; and dopingportions of said channel layer not shielded by exposing the portions toa reagent selected to yield a chemical reaction with said compoundsemiconductor material causing removal of a component of saidsemiconductor material thereby to change its electrical properties anddefine said doped source and drain regions.
 8. The method of claim 7wherein said semiconductor material is formed of CdSe and said reagentis in the form of a hydrogen plasma.
 9. The method of claim 7 whereinsaid semiconductor material is formed of one of CdSe, CdTe, CdS, InP andGaP.
 10. The method of claim 7 wherein said reagent is in the form ofone of a gas, plasma and liquid chemical reagent.
 11. In a method offorming a self-aligned thin film transistor, wherein a gate insulatinglayer covers a gate electrode and a surface of a glass substrate, saidmethod comprising the steps of:depositing a channel layer formed ofcompound semiconductor material on said gate insulating layer, saidchannel layer being positioned over and extending beyond said gateelectrode; forming a shield over a portion of the channel layer alignedwith and overlying said gate electrode; subjecting the structure to areagent selected to react with said semiconductor material causingremoval of a component thereof, said reagent reacting with the portionsof said channel layer not covered by said shield to form doped sourceand drain regions extending to the edges of said gate electrode andpositioned on opposite sides of a channel; and forming source and drainelectrodes in contact with said respective source and drain regions. 12.The method of claim 11 wherein said semiconductor material is formed ofCdSe and said reagent is in the form of a hydrogen plasma.
 13. Themethod of claim 11 wherein said semiconductor material is formed of oneof CdSe, CdTe, CdS, InP and GaP.
 14. The method of claim 11 wherein saidreagent is in the form of one of a gas, plasma and liquid chemicalreagent.